DBGHALT=NORMAL, TIMEROVRFLOWPERIOD=CYCLES2, REFRESHPERIOD=CYCLES2, REFRSEL=V125, CH0PRESCRST=NORESETPRESC, SINEMODE=DISSINEMODE, DIFF=SINGLEENDED
No Description
| DIFF | Differential Mode 0 (SINGLEENDED): Single ended output 1 (DIFFERENTIAL): Differential output |
| SINEMODE | Sine Mode 0 (DISSINEMODE): Sine mode disabled. Sine reset to 0 degrees 1 (ENSINEMODE): Sine mode enabled |
| SINERESET | Sine Wave Reset When inactive |
| CH0PRESCRST | Channel 0 Start Reset Prescaler 0 (NORESETPRESC): Prescaler not reset on channel 0 start 1 (RESETPRESC): Prescaler reset on channel 0 start |
| REFRSEL | Reference Selection 0 (V125): Internal 1.25 V bandgap reference 1 (V25): Internal 2.5 V bandgap reference 2 (VDD): AVDD reference 3 (EXT): External pin reference |
| PRESC | Prescaler Setting for DAC clock |
| TIMEROVRFLOWPERIOD | Internal Timer Overflow Period 0 (CYCLES2): The Timer overflows every 2 Prescaled CLK_DAC cycles 1 (CYCLES4): The Timer overflows every 4 Prescaled CLK_DAC cycles 2 (CYCLES8): The Timer overflows every 8 Prescaled CLK_DAC cycles 3 (CYCLES16): The Timer overflows every 16 Prescaled CLK_DAC cycles 4 (CYCLES32): The Timer overflows every 32 Prescaled CLK_DAC cycles 5 (CYCLES64): The Timer overflows every 64 Prescaled CLK_DAC cycles |
| REFRESHPERIOD | Refresh Timer Overflow Period 0 (CYCLES2): All channels with enabled refresh are refreshed every 2 CLK_REFRESH cycles 1 (CYCLES4): All channels with enabled refresh are refreshed every 4 CLK_REFRESH cycles 2 (CYCLES8): All channels with enabled refresh are refreshed every 8 CLK_REFRESH cycles 3 (CYCLES16): All channels with enabled refresh are refreshed every 16 CLK_REFRESH cycles 4 (CYCLES32): All channels with enabled refresh are refreshed every 32 CLK_REFRESH cycles 5 (CYCLES64): All channels with enabled refresh are refreshed every 64 CLK_REFRESH cycles 6 (CYCLES128): All channels with enabled refresh are refreshed every 128 CLK_REFRESH cycles 7 (CYCLES256): All channels with enabled refresh are refreshed every 256 CLK_REFRESH cycles |
| BIASKEEPWARM | Bias Keepwarm Mode Enable |
| DMAWU | VDAC DMA Wakeup |
| ONDEMANDCLK | Always allow clk_dac |
| DBGHALT | Debug Halt 0 (NORMAL): Continue operation as normal during debug mode 1 (HALT): Complete the current conversion and then halt during debug mode |
| WARMUPTIME | DAC Warmup Time |